tag: Mentor

Blog Review: June 4
By Jesse Allen - 04 Jun, 2025 - Comments: 0

In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the implications of the software-defined transition, how it affects semiconductor development, and why it seems to be leading more companies towards developing their own silicon. Cadence’s Vinod Khera shows off a Linux-based audio development platform for prototyping AI audio applications with support for real-time ... » read more

Connecting AI Accelerators
By Ann Mutschler - 04 Jun, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering sat down to discuss the various ways that AI accelerators are being applied today with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vice president of marketing at Expedera; Alexander Petr, senior director at Keysight; Steve Roddy, chief marketing office... » read more

Chip Industry Week in Review
By The SE Staff - 30 May, 2025 - Comments: 1

The U.S. Commerce Department is tightening controls on EDA software sold to China by imposing additional license requirements. EDA companies are assessing the impact. Details on how broad the restrictions will be are still pending. The U.S. Federal Trade Commission (FTC) will require Synopsys and Ansys to divest key software assets — including optical, photonic, and RTL power analysis tool... » read more

Addressing Stress In Heterogeneous 3D-IC Designs
By Shetha Nolke - 29 May, 2025 - Comments: 0

The benefits of 3D IC architectures are well-documented – smaller footprints, lower power, and increased performance. However, the move to heterogeneous 3D designs also introduces a host of new challenges that must be carefully navigated. As chip designers integrate multiple dies and technologies into a single 3D package, the interactions between the chip and package become increasingly co... » read more

Optimizing Data Movement
By Ann Mutschler - 29 May, 2025 - Comments: 1

Demand for new and better AI models is creating an insatiable demand for more processing power and much better data throughput, but it's also creating a slew of new challenges for which there are not always good solutions. The key here is figuring out where bottlenecks might crop up in complex chips and advanced packages. This involves a clear understanding of how much bandwidth is required ... » read more

Executive Outlook: Chiplets, 3D-ICs, and AI
By Ed Sperling - 29 May, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product ... » read more

Thermo-Mechanical Stress On Active Chiplets In A 3D-IC Heterogeneous Package Assembly
By Siemens EDA - 29 May, 2025 - Comments: 0

The move to heterogeneous multi-chip/chiplet products improves yield, performance and modularity while reducing power and overall product footprint. However, this shift to heterogeneous assembly also introduces new complexities that can influence chip warpage and circuit behavior due to thermo-mechanical stress impacts. In heterogeneous 3D IC architectures, the interaction between the chips ... » read more

Blog Review: May 28
By Jesse Allen - 28 May, 2025 - Comments: 0

Siemens’ Patrick Hope considers how to fully perform post-route signal integrity verification on PCB designs while maintaining the project’s timeline by implementing a progressive verification methodology that enables signal integrity experts to focus on issues that demand their expertise rather than simple errors. Cadence’s Vanessa Do checks out how CXL addresses the constant demand f... » read more

Chip Industry Week in Review
By The SE Staff - 23 May, 2025 - Comments: 0

Podcast: imec's roadmap and a one-on-one interview with the European research house's chief strategy officer. China's Xiaomi debuted an in-house-designed 10-core mobile SoC built on a 3nm process. The company did not identify the foundry. It also announced plans to invest 50 billion yuan (~$7B) over the next decade to develop high-end smartphone chips, as part of a 200 billion yuan (~$28B) c... » read more

Future-proofing AI Models
By Ann Mutschler - 21 May, 2025 - Comments: 0

Experts At The Table: Making sure AI accelerators can be updated for future requirements is becoming essential due to the rapid introduction of new models. Semiconductor Engineering sat down to discuss the challenges of future-proofing these designs with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vic... » read more

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